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1/38 product preview april 2002 this is preliminary information on a new product now in development. details are subject to change without notice. m29w641d 64 mbit (4mb x16, uniform block) 3v supply flash memory features summary n supply voltage Cv cc = 2.7v to 3.6v core power supply Cv ccq = 1.8v to 3.6v for input/output Cv pp =12 v for fast program (optional) n access time: 70, 90 ns n programming time C 10 s typical C double word programming option n 128 main memory blocks C 32 kwords each n jedec standard command set n program/erase controller C embedded program and erase algorithms n erase suspend and resume modes C read and program another block during erase suspend n unlock bypass program command C faster production/batch programming n v pp pin for fast program n w p pin for write protect of first or last block n temporary block unprotection mode n common flash interface (cfi) n extended memory block C extra block used as security block or to store additional information n low power consumption C standby and automatic standby n 100,000 program/erase cycles per block n electronic signature C manufacturer code: 0020h C device code m29w641d: 22c7h figure 1. packages tsop48 (n) 12 x 20mm
m29w641d 2/38 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. tsop connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 address inputs (a0-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data inputs/outputs (dq8-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write protect (wp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 reset/block temporary unprotect (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 v pp (v pp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v cc supply voltage (2.7v to 3.6v).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ccq supply voltage (1.8v to 3.6v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 block protect and chip unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 block protect and chip unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 read/reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 auto select command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 unlock bypass command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 unlock bypass program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 unlock bypass reset command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 chip erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 block erase command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 erase suspend command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 erase resume command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 enter extended block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3/38 m29w641d exit extended block command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . 13 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 alternative toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. operating and ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 table 8. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 table 10. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. reset/block temporary unprotect ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. accelerated program timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 tsop48 C 48 lead plastic thin small outline, 12 x 20mm, package outline . . . . . . . . . . . . . . . . 23 tsop48 C 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . . . . . . . . 23 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 appendix a. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 table 16. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
m29w641d 4/38 appendix b. common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 18. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 19. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 21. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 22. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 appendix c. block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 23. programmer technique bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13. programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15. in-system equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5/38 m29w641d summary description the m29w641d is a 64 mbit (4mb x16) non-vola- tile memory that can be read, erased and repro- grammed. these operations can be performed using a single low voltage (2.7 to 3.6v) supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. v ccq allows to drive the i/o pin down to 1.8 v. an optional 12 v v pp power supply is provided to speed up customer programming. first or last block can be protected from accidental programming or erasure (if wp =vil). each block can be erased independently so it is possible to preserve valid data while old data is erased. the blocks can be protected to prevent accidental program or erase commands from modifying the memory. program and erase com- mands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special op- erations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identi- fied. the command set required to control the memory is consistent with jedec standards. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is delivered with all the bits erased (set to 1). figure 2. logic diagram table 1. signal names a0-a21 address inputs dq0-dq7 data inputs/outputs dq8-dq15 data inputs/outputs e chip enable g output enable w write enable rp reset/block temporary unprotect w p write protect v cc supply voltage v ccq supply voltage for input/output v pp supply voltage for fast program (optional) v ss ground ai06697 22 a0-a21 w dq0-dq15 v cc m29w641d e v ss 16 g rp v pp wp v ccq
m29w641d 6/38 figure 3. tsop connections dq3 dq9 dq2 a6 dq0 w a3 a19 dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15 v cc dq4 dq5 a7 dq7 wp v pp m29w641d 12 1 13 24 25 36 37 48 dq8 a20 a21 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 v ccq a15 a14 v ss e a0 rp v ss ai06698
7/38 m29w641d signal descriptions see figure 2, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a21). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data inputs/outputs (dq0-dq7). the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state ma- chine. data inputs/outputs (dq8-dq15). the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memorys com- mand interface. write protect (w p ). the write protect pin pro- vides a hardware method of protecting either the first or last block. the write protect pin must not be left floating or unconnected. when write protect is low, v il , the memory pro- tects either the first or last block; program and erase operations in this block are ignored while write protect is low. when write protect is high, v ih , the memory re- verts to the previous protection status for this block. program and erase operations can now modify the data in this block unless the block is protected using block protection. reset/block temporary unprotect (rp ). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. note that if write protect (wp ) is at v il , then one of the two outermost blocks will remain protected even if rp is at v id . a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 13 and figure 11, reset/ block temporary unprotect ac characteristics, for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . v pp (v pp ). when the v pp pin is raised to v pp the memory automatically enters the unlock bypass mode. when the pin is returned to v ih or v il nor- mal operation resumes. during unlock bypass program operations the memory draws i pp from the pin to supply the programming circuits. see the description of the unlock bypass command in the command interface section. the transitions from v ih to v pp and from v pp to v ih must be slower than t vhvpp , see figure 12. never raise the pin to v pp from any mode except read mode, otherwise the memory may be left in an indeterminate state. a 0.1f capacitor should be connected between the v pp pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program, i pp . v cc supply voltage (2.7v to 3.6v). v cc pro- vides the power supply for all operations (read, program and erase). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . v ccq supply voltage (1.8v to 3.6v). v ccq pro- vides the power supply for input and output. v ss ground. v ss is the reference for all voltage measurements.
m29w641d 8/38 table 2. bus operations note: x = v il or v ih . operation e g w address inputs a0-a21 data inputs/outputs dq15-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih x hi-z standby v ih x x x hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 0020h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih 22c7h extended memoryblock verify code v il v il v ih a0 = v ih , a1 = v ih , a6 = v il , a9 = v id , others v il or v ih 98h (factory locked, wp protects highest block) 18h (not factory locked, wp protects highest block) 88h (factory locked, wp protects lowest block) 08h (not factory locked, wp protects lowest block)
9/38 m29w641d bus operations there are five standard bus operations that control the device. these are bus read, bus write, out- put disable, standby and automatic standby. see table 2, bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not af- fect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 8, read mode ac waveforms, and table 10, read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figure 9 and figure 10, write ac waveforms, and table 11 and table 12, write ac characteristics, for details of the timing re- quirements. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 9, dc characteristics. during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 300ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in table 2, bus operations. block protect and chip unprotect. groups of blocks can be protected against accidental pro- gram or erase. the whole chip can be unprotected to allow the data inside the blocks to be changed. write protect (wp ) can be used to protect one of the outermost blocks. when write protect (wp ) is at v il one of the two outermost blocks is protect- ed and remains protected regardless of the block protection status or the reset/block temporary unprotect pin status. for the M29W641DH, it is the highest addressed block that can be protect- ed. for the m29w641dl, it is the lowest. block protect and chip unprotect operations are described in appendix c.
m29w641d 10/38 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. see table 3 for a summary of the commands. read/reset command. the read/reset command returns the memory to its read mode where it behaves like a rom or eprom. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, be- tween bus write cycles before the start of a pro- gram or erase operation, to return the device to read mode. if the read/reset command is issued during the timeout of a block erase operation then the memory will take up to 10s to abort. during the abort period no valid data can be read from the memory. the read/reset command will not abort an erase operation when issued while in erase suspend. auto select command. the auto select command is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are required to issue the auto se- lect command. once the auto select command is issued the memory remains in auto select mode until a read/reset command is issued. read cfi query and read/reset commands are accepted in auto select mode, all other commands are ig- nored. in auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for st- microelectronics is 0020h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29w641d is 22c7h. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a12-a21 specifying the address of the block. the other address bits may be set to ei- ther v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0- dq7, otherwise 00h is output. read cfi query command. the read cfi query command is used to read data from the common flash interface (cfi) memory area. this command is valid when the de- vice is in the read array mode, or when the device is in autoselected mode. one bus write cycle is required to issue the read cfi query command. once the command is is- sued subsequent bus read operations read from the common flash interface memory area. the read/reset command must be issued to re- turn the device to the previous mode (the read ar- ray mode or autoselected mode). a second read/ reset command would be needed if the device is to be put in the read array mode from autoselect- ed mode. see appendix b, table 17 to table 22 for details on the information contained in the common flash interface (cfi) memory area. program command. the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write oper- ations, the final write operation latches the ad- dress and data in the internal state machine and starts the program/erase controller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 4. bus read op- erations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. note that the program command cannot change a bit set at 0 back to 1. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from 0 to 1. fast program commands there is a fast program command available to im- prove the programming throughput, by writing sev- eral adjacent words or bytes in parallel: the double word program command. double word program command. the double word program command is used to write a page of two adjacent words in parallel. the two words must differ only for the address a0. three bus write cycles are necessary to issue the double word program command.
11/38 m29w641d n the first bus cycle sets up the double word program command. n the second bus cycle latches the address and the data of the first word to be written. n the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. only one bank can be programmed at any one time. the other bank must be in read mode or erase suspend. programming should not be attempted when v pp is not at v pph . after programming has started, bus read opera- tions in the bank being programmed output the status register content, while bus read opera- tions to the other bank output the contents of the memory array. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the bank where the command was issued will continue to output the status reg- ister. a read/reset command must be issued to reset the error condition and return to read mode. note that the fast program commands cannot change a bit set at 0 back to 1. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1. typical program times are given in table 4, pro- gram, erase times and program, erase endur- ance cycles. unlock bypass command. the unlock bypass command is used in conjunc- tion with the unlock bypass program command to program the memory faster than with the standard program commands. when the cycle time to the device is long (as with some eprom program- mers) considerable time saving can be made by using these commands. three bus write opera- tions are required to issue the unlock bypass command. once the unlock bypass command has been is- sued the memory will only accept the unlock by- pass program command and the unlock bypass reset command. the memory can be read as if in read mode. when v pp is applied to the v pp pin the memory automatically enters the unlock bypass mode and the unlock bypass program command can be is- sued immediately. unlock bypass program command. the unlock bypass command is used in conjunc- tion with the unlock bypass program command to program the memory. when the cycle time to the device is long (as with some eprom program- mers) considerable time saving can be made by using these commands. three bus write opera- tions are required to issue the unlock bypass command. once the unlock bypass command has been is- sued the memory will only accept the unlock by- pass program command and the unlock bypass reset command. the memory can be read as if in read mode. the memory offers accelerated program opera- tions through the v pp pin. when the system as- serts v pp on the v pp pin, the memory automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the memo- ry uses the higher voltage on the v pp pin, to accel- erate the unlock bypass program operation. never raise the v pp pin to v pp from any mode ex- cept read mode, otherwise the memory may be left in an indeterminate state. unlock bypass reset command. the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/ reset command does not exit from unlock bypass mode. chip erase command. the chip erase command can be used to erase the entire chip. six bus write operations are re- quired to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation ap- pears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands, including the erase suspend com- mand. it is not possible to issue any command to abort the operation. typical chip erase times are given in table 4. all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the sec- tion on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to 1. all previous data is lost.
m29w641d 12/38 block erase command. the block erase command can be used to erase a list of one or more blocks. six bus write opera- tions are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each addition- al block must therefore be selected within 50s of the last block. the 50s timer restarts when an ad- ditional block is selected. the status register can be read after the sixth bus write operation. see the status register section for details on how to identify if the program/erase controller has start- ed the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command. typical block erase times are given in table 4. all bus read operations during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within 50 s of the erase suspend command being is- sued. once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start im- mediately when the erase resume command is issued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. read- ing from blocks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be ac- cepted. erase resume command. the erase resume command must be used to re- start the program/erase controller after an erase suspend. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once. enter extended block command the device has an extra 32 kword block (extend- ed block) that can only be accessed using the en- ter extended block command. three bus write cycles are required to issue the extended block command. once the command has been issued the device enters extended block mode where all bus read or write operations to the boot block addresses access the extended block. therefore in extended block mode the boot blocks are not accessible. all commands are accepted by the command interface. to exit from the extended block mode the exit ex- tended block command must be issued. the extended block can be protected, however once protected the protection cannot be undone. exit extended block command. the exit extended block command is used to exit from the extended block mode and return the de- vice to read mode. four bus write operations are required to issue the command. block protect and chip unprotect commands. groups of blocks can be protected against acci- dental program or erase. the whole chip can be unprotected to allow the data inside the blocks to be changed. block protect and chip unprotect operations are described in appendix c.
13/38 m29w641d table 3. commands note: x dont care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. table 4. program, erase times and program, erase endurance cycles note: 1. t a = 25c, v cc = 3.3v. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd double word program 3 555 50 pa0 pd0 pa1 pd1 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2x a0papd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 read cfi query 1 55 98 enter extended block 3 555 aa 2aa 55 555 88 exit extended block 4 555 aa 2aa 55 555 90 x 00 parameter min typ (1) typical after 100k w/e cycles (1) max unit chip erase 80 80 400 s block erase (32 kwords) 0.8 6 s program (word) 10 200 s double word program 10 200 s chip program (word by word) 40 200 s chip program (double word) 10 100 s program/erase cycles (per block) 100,000 cycles
m29w641d 14/38 status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase sus- pend when an address within a block being erased is accessed. the bits in the status register are summarized in table 5, status register bits. data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts 0, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a 1 during a bus read operation within a block being erased. the data polling bit will change from a 0 to a 1 when the program/erase controller has suspended the erase operation. figure 4, data polling flowchart, gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from 0 to 1 to 0, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 5, data toggle flowchart, gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to 1 when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to 0 back to 1 and attempting to do so will set dq5 to 1. a bus read operation to that ad- dress will show the bit is still 0. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1. erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to 1. before the program/erase controller starts the erase timer bit is set to 0 and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from 0 to 1 to 0, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly.
15/38 m29w641d table 5. status register bits note: unspecified data bits should be ignored. figure 4. data polling flowchart figure 5. data toggle flowchart operation address dq7 dq6 dq5 dq3 dq2 program any address dq7 toggle 0 CC program during erase suspend any address dq7 toggle 0 C C program error any address dq7 toggle 1 C C chip erase any address 0 toggle 0 1 toggle block erase before timeout erasing block 0 toggle 0 0 toggle non-erasing block 0 toggle 0 0 no toggle block erase erasing block 0 toggle 0 1 toggle non-erasing block 0 toggle 0 1 no toggle erase suspend erasing block 1 no toggle 0 C toggle non-erasing block data read as normal erase error good block address 0 toggle 1 1 no toggle faulty block address 0 toggle 1 1 toggle read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai90194 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq6 start read dq6 twice fail pass ai90195 dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
m29w641d 16/38 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 6. absolute maximum ratings note: 1. minimum voltage may undershoot to C2v during transition and for less than 20ns during transitions. 2. maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. 3. v pp must not remain at 12v for more than a total of 80hrs. symbol parameter min max unit t bias temperature under bias C50 125 c t stg storage temperature C65 150 c v io input or output voltage (1,2) C0.6 v cc +0.6 v v cc supply voltage C0.6 4 v v id identification voltage C0.6 13.5 v v pp (3) program voltage C0.6 13.5 v
17/38 m29w641d dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 7. operating and ac measurement conditions figure 6. ac measurement i/o waveform figure 7. ac measurement load circuit table 8. device capacitance note: sampled only, not 100% tested. parameter m29w641d unit 70 90 min max min max v cc supply voltage 3.0 3.6 2.7 3.6 v ambient operating temperature C40 85 C40 85 c load capacitance (c l ) 30 30 pf input rise and fall times 10 10 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v ai05557 v cc 0v v cc /2 ai05558 c l c l includes jig capacitance device under test 25k w v cc 25k w v cc 0.1f v pp 0.1f symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
m29w641d 18/38 table 9. dc characteristics note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6 mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v 100 a i cc3 supply current (program/ erase) program/erase controller active v pp pin = v il or v ih 20 ma v pp pin = v pp 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v pp voltage for v pp program acceleration v cc = 3.0v 10% 11.5 12.5 v i pp current for v pp program acceleration v cc = 3.0v 10% 15 ma v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = C100 a v cc C 0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 a v lko (1) program/erase lockout supply voltage 1.8 2.3 v
19/38 m29w641d figure 8. read mode ac waveforms table 10. read ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29w641d unit 70 90 t avav t rc address valid to next address valid e = v il , g = v il min 70 90 ns t avqv t acc address valid to output valid e = v il , g = v il max 70 90 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g = v il max 70 90 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 30 35 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 25 30 ns t ghqz (1) t df output enable high to output hi-z e = v il max 25 30 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns ai06699 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a21 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid
m29w641d 20/38 figure 9. write ac waveforms, write enable controlled table 11. write ac characteristics, write enable controlled symbol alt parameter m29w641d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 50 ns t dvwh t ds input valid to write enable high min 45 50 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 50 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t vchel t vcs v cc high to chip enable low min 50 50 s ai06800 e g w a0-a21 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl
21/38 m29w641d figure 10. write ac waveforms, chip enable controlled table 12. write ac characteristics, chip enable controlled symbol alt parameter m29w641d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 50 ns t dveh t ds input valid to chip enable high min 45 50 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 50 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t vchwl t vcs v cc high to write enable low min 50 50 s ai06801 e g w a0-a21 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel
m29w641d 22/38 figure 11. reset/block temporary unprotect ac waveforms table 13. reset/block temporary unprotect ac characteristics note: 1. sampled only, not 100% tested. figure 12. accelerated program timing waveforms symbol alt parameter m29w641d unit 70 90 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 ns t plpx t rp rp pulse width min 500 500 ns t phphh (1) t vidr rp rise time to v id min 500 500 ns t vhvpp (1) v pp rise and fall time min 250 250 ns ai06802 w, rp tplpx tphwl, tphel, tphgl tphphh e, g ai06806 v pp pin v pp v il or v ih tvhvpp tvhvpp
23/38 m29w641d package mechanical tsop48 C 48 lead plastic thin small outline, 12 x 20mm, package outline note: drawing is not to scale. tsop48 C 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 11.90 12.10 0.4685 0.4764 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0279 a 0 5 0 5 n48 48 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
m29w641d 24/38 part numbering table 14. ordering information scheme devices are shipped from the factory with the memory content bits erased to 1. for a list of available op- tions (speed, package, etc...) or for further information on any aspect of this device, please contact your nearest st sales office. example: m29w641d l 70 n 1 t device type m29 operating voltage w = v cc = 2.7 to 3.6v device function 641d = 64 mbit (x16), uniform block array matrix h = protection on highest address block l = protection on lowest address block speed 70 = 70 ns 90 = 90 ns package n = tsop48: 12 x 20 mm temperature range 1 = 0 to 70 c 6 = C40 to 85 c option t = tape & reel packing
25/38 m29w641d revision history table 15. document revision history date version revision details 30-apr-2002 -01 document released
m29w641d 26/38 appendix a. block addresses table 16. block addresses block kwords protection block group address range 032 protection group 000000hC007fffh (1) 1 32 008000hC00ffffh 2 32 010000hC017fffh 3 32 018000hC01ffffh 432 protection group 020000hC027fffh 5 32 028000hC02ffffh 6 32 030000hC037fffh 7 32 038000hC03ffffh 832 protection group 040000hC047fffh 9 32 048000hC04ffffh 10 32 050000hC057fffh 11 32 058000hC05ffffh 12 32 protection group 060000hC067fffh 13 32 068000hC06ffffh 14 32 070000hC077fffh 15 32 078000hC07ffffh 16 32 protection group 080000hC087fffh 17 32 088000hC08ffffh 18 32 090000hC097fffh 19 32 098000hC09ffffh 20 32 protection group 0a0000hC0a7fffh 21 32 0a8000hC0affffh 22 32 0b0000hC0b7fffh 23 32 0b8000hC0bffffh 24 32 protection group 0c0000hC0c7fffh 25 32 0c8000hC0cffffh 26 32 0d0000hC0d7fffh 27 32 0d8000hC0dffffh 28 32 protection group 0e0000hC0e7fffh 29 32 0e8000hC0effffh 30 32 0f0000hC0f7fffh 31 32 0f8000hC0fffffh
27/38 m29w641d 32 32 protection group 100000hC107fffh 33 32 108000hC10ffffh 34 32 110000hC117fffh 35 32 118000hC11ffffh 36 32 protection group 120000hC127fffh 37 32 128000hC12ffffh 38 32 130000hC137fffh 39 32 138000hC13ffffh 40 32 protection group 140000hC147fffh 41 32 148000hC14ffffh 42 32 150000hC157fffh 43 32 158000hC15ffffh 44 32 protection group 160000hC167fffh 45 32 168000hC16ffffh 46 32 170000hC177fffh 47 32 178000hC17ffffh 48 32 protection group 180000hC187fffh 49 32 188000hC18ffffh 50 32 190000hC197fffh 51 32 198000hC19ffffh 52 32 protection group 1a0000hC1a7fffh 53 32 1a8000hC1affffh 54 32 1b0000hC1b7fffh 55 32 1b8000hC1bffffh 56 32 protection group 1c0000hC1c7fffh 57 32 1c8000hC1cffffh 58 32 1d0000hC1d7fffh 59 32 1d8000hC1dffffh 60 32 protection group 1e0000hC1e7fffh 61 32 1e8000hC1effffh 62 32 1f0000hC1f7fffh 63 32 1f8000hC1fffffh 64 32 protection group 200000hC207fffh 65 32 208000hC20ffffh 66 32 210000hC217fffh 67 32 218000hC21ffffh block kwords protection block group address range
m29w641d 28/38 68 32 protection group 22 0000hC227fffh 69 32 228000hC22ffffh 70 32 230000hC237fffh 71 32 238000hC23ffffh 72 32 protection group 240000hC247fffh 73 32 248000hC24ffffh 74 32 250000hC257fffh 75 32 258000hC25ffffh 76 32 protection group 260000hC267fffh 77 32 268000hC26ffffh 78 32 270000hC277fffh 79 32 278000hC27ffffh 80 32 protection group 280000hC287fffh 81 32 288000hC28ffffh 82 32 290000hC297fffh 83 32 298000hC29ffffh 84 32 protection group 2a0000hC2a7fffh 85 32 2a8000hC2affffh 86 32 2b0000hC2b7fffh 87 32 2b8000hC2bffffh 88 32 protection group 2c0000hC2c7fffh 89 32 2c8000hC2cffffh 90 32 2d0000hC2d7fffh 91 32 2d8000hC2dffffh 92 32 protection group 2e0000hC2e7fffh 93 32 2e8000hC2effffh 94 32 2f0000hC2f7fffh 95 32 2f8000hC2fffffh 96 32 protection group 300000hC307fffh 97 32 308000hC30ffffh 98 32 310000hC317fffh 99 32 318000hC31ffffh 100 32 protection group 320000hC327fffh 101 32 328000hC32ffffh 102 32 330000hC337fffh 103 32 338000hC33ffffh block kwords protection block group address range
29/38 m29w641d note: 1. used as the extended block addresses in extended block mode. 104 32 protection group 34 0000hC347fffh 105 32 348000hC34ffffh 106 32 350000hC357fffh 107 32 358000hC35ffffh 108 32 protection group 360000hC367fffh 109 32 368000hC36ffffh 110 32 370000hC377fffh 111 32 37 8000hC37ffffh 112 32 protection group 38 0000hC387fffh 113 32 388000hC38ffffh 114 32 390000hC397fffh 115 32 398000hC39ffffh 116 32 protection group 3a0000hC3a7fffh 117 32 3a8000hC3affffh 118 32 3b0000hC3b7fffh 119 32 3b8000hC3bffffh 120 32 protection group 3c0000hC3c7fffh 121 32 3c8000hC3cffffh 122 32 3d0000hC3d7fffh 123 32 3d8000hC3dffffh 124 32 protection group 3e0000hC3e7fffh 125 32 3e8000hC3effffh 126 32 3f0000hC3f7fffh 127 32 3f8000hC3fffffh block kwords protection block group address range
m29w641d 30/38 appendix b. common flash interface (cfi) the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command is issued the de- vice enters cfi query mode and the data structure is read from the memory. table 17 to table 22 show the addresses used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 22, security code area). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. table 17. query structure overview note: query data are always presented on the lowest order data outputs. table 18. cfi query identification string note: query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are 0. address sub-section name description 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout 40h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h security code area 64 bit unique device number address data description value 10h 0051h q 11h 0052h query unique ascii string "qry" "r" 12h 0059h "y" 13h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 0000h 15h 0040h address for primary algorithm extended query table (see table 20) p = 40h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 0000h 19h 0000h address for alternate algorithm extended query table na 1ah 0000h
31/38 m29w641d table 19. cfi query system interface information table 20. device geometry definition address data description value 1bh 0027h v cc logic supply minimum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 2.7v 1ch 0036h v cc logic supply maximum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 3.6v 1dh 00b5h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.5v 1eh 00c5h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.5v 1fh 0004h typical timeout per single word program = 2 n s 16s 20h 0000h typical timeout for minimum size write buffer program = 2 n s na 21h 000ah typical timeout per individual block erase = 2 n ms 1s 22h 0000h typical timeout for full chip erase = 2 n ms na 23h 0004h maximum timeout for word program = 2 n times typical 256 s 24h 0000h maximum timeout for write buffer program = 2 n times typical na 25h 0003h maximum timeout per individual block erase = 2 n times typical 8s 26h 0000h maximum timeout for chip erase = 2 n times typical na address data description value 27h 0017h device size = 2 n in number of bytes 8 mbyte 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0000h 0000h maximum number of bytes in multi-byte program or page = 2 n na 2ch 0001h number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 1 2dh 2eh 003eh 0000h region 1 information number of identical size erase block = 003eh+1 64 2fh 30h 0000h 0000h region 1 information block size in region 1 = 0100h * 256 byte 64 kbyte
m29w641d 32/38 table 21. primary algorithm-specific extended query table table 22. security code area address data description value 40h 0050h primary algorithm extended query table unique ascii string pri "p" 41h 0052h "r" 42h 0049h "i" 43h 0031h major version number, ascii "1" 44h 0030h minor version number, ascii "0" 45h 0000h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) ye s 46h 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 0004h block protection 00 = not supported, x = number of sectors per protection group 4 48h 0001h temporary block unprotect 00 = not supported, 01 = supported ye s 49h 0004h block protect /unprotect 04 = m29w400b 4 4ah 0000h simultaneous operations, 00 = not supported no 4bh 0000h burst mode, 00 = not supported, 01 = supported no 4ch 0000h page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word no 4dh 00b5h v pp supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.5v 4eh 00c5h v pp supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.5v address data description 61h xxxx 64 bit: unique device number 62h xxxx 63h xxxx 64h xxxx
33/38 m29w641d appendix c. block protection block protection can be used to prevent any oper- ation from modifying the data stored in the memo- ry. once protected, program and erase operations within the protected group fail to change the data. there are three techniques that can be used to control block protection, these are the program- mer technique, the in-system technique and tem- porary unprotection. temporary unprotection is controlled by the reset/block temporary unpro- tection pin, rp ; this is described in the signal de- scriptions section. to protect the extended block issue the enter ex- tended block command and then use either the programmer or in-system technique. once pro- tected issue the exit extended block command to return to read mode. the extended block protec- tion is irreversible, once protected the protection cannot be undone. programmer technique the programmer technique uses high (v id ) volt- age levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a group of blocks follow the flowchart in figure 13, programmer equipment group protect flowchart. to unprotect the whole chip it is neces- sary to protect all of the groups first, then all groups can be unprotected at the same time. to unprotect the chip follow figure 14, programmer equipment chip unprotect flowchart. table 23, programmer technique bus operations, gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp . this can be achieved without violating the maximum ratings of the components on the micro- processor bus, therefore this technique is suitable for use after the memory has been fitted to the sys- tem. to protect a group of blocks follow the flowchart in figure 15, in-system equipment group protect flowchart. to unprotect the whole chip it is neces- sary to protect all of the groups first, then all the groups can be unprotected at the same time. to unprotect the chip follow figure 16, in-system equipment chip unprotect flowchart. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the pro- cedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. table 23. programmer technique bus operations note: 1. block protection groups are shown in appendix a, tables 16. operation e g w address inputs a0-a21 data inputs/outputs dq15-dq0 block (group) protect (1) v il v id v il pulse a9 = v id , a12-a21 block address others = x x chip unprotect v id v id v il pulse a9 = v id , a12 = v ih , a15 = v ih others = x x block (group) protection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v il , a9=v id , a12-a21 block address others = x pass = xx01h retry = xx00h block (group) unprotection verify v il v il v ih a0 = v il , a1 = v ih , a6 = v ih , a9 = v id , a12-a21 block address others = x retry = xx01h pass = xx00h
m29w641d 34/38 figure 13. programmer equipment group protect flowchart address = group address ai05574 g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a0, a6 = v il , a1 = v ih a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
35/38 m29w641d figure 14. programmer equipment chip unprotect flowchart protect all groups ai05575 a6, a12, a15 = v ih (1) e, g, a9 = v id data w = v ih e, g = v ih address = current group address a0 = v il , a1, a6 = v ih wait 10ms = 00h increment current group n = 0 current group = 0 wait 4s w = v il ++n = 1000 start yes yes no no last group yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
m29w641d 36/38 figure 15. in-system equipment group protect flowchart ai05576 write 60h address = group address a0 = v il , a1 = v ih , a6 = v il n = 0 wait 100s write 40h address = group address a0 = v il , a1 = v ih , a6 = v il rp = v ih ++n = 25 start fail pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = group address a0 = v il , a1 = v ih , a6 = v il rp = v id issue read/reset command issue read/reset command write 60h address = group address a0 = v il , a1 = v ih , a6 = v il
37/38 m29w641d figure 16. in-system equipment chip unprotect flowchart ai05577 write 60h any address with a0 = v il , a1 = v ih , a6 = v ih n = 0 current group = 0 wait 10ms write 40h address = current group address a0 = v il , a1 = v ih , a6 = v ih rp = v ih ++n = 1000 start fail pass yes no data = 00h yes no rp = v ih wait 4s read data address = current group address a0 = v il , a1 = v ih , a6 = v ih rp = v id issue read/reset command issue read/reset command protect all groups increment current group last group yes no write 60h any address with a0 = v il , a1 = v ih , a6 = v ih verify unprotect set-up end
m29w641d 38/38 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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